Memory

Memory Map

OM6XXX memory consists of ROM, EFUSE, RAM, external SPI Flash. Cache have dedicated RAM. The memory map is shown as follow:

Memory Map

ROM

The ROM code is located at [0x00100000, 0x00104000), in which Bootloader, BT Stack, Flash Driver and other platform modules are built.

EFUSE

he EFUSE size is 256 bits, and uses the following APIs for reading and writing operations (reference: drv_efuse.h), n which user safety key (128bits,addr=0) and system CP/FT calibration data (128bits,addr=16) is stored.

void drv_efuse_write(uint32_t addr, const void *data, uint32_t length);
void drv_efuse_read(uint32_t addr, void *data, uint32_t length);

Note

About efuse writing function, please be careful.

RAM

The RAM located at [0x20000000, 0x20014000), and base address 0x00200000 also points to this RAM.

CACHE

OM6XXX has a 8K bytes cache, and it co-works with SPI Flash Controller to speed up the SPI Flash read.

Alias Address

In the current SDK, the ROM is remaped as alias address, and located at [0x00000000, 0x00004000)

Flash Description

Different from RAM which can be read / written directly，flash is a kind of non-volatile storage for code shadowing to RAM, executing code directly, or storing data. Flash must be empty or erased before written into.

If flash access just needs single mode with read / program / erase, there are lots of flash models meeting the requirement. If Dual / Quad modes and other enhanced functions are required, such as flash Deep Power-down (DP) for power saving, or software Block Protect (BP) for flash program / erase protection, choosing flash model from Approved Vendor List provided by Onmicro is strongly suggested.

In order to enhance the performance, high speed read mechanism is also available in the flash driver. OM6XXX supports executing code (XIP) on SPI Flash, but there are also some limitations and precautions.

There are three basic operations for flash read, write, and erase operations.

Note

All flash APIs are not calling in IRQ.

Internal SPI Flash

OM6XXX has internal SPI Flash, its cachable address is located at [0x00400000,0x00800000), and non-cachable address is in [0x50000000,0x51000000).

The flash is divided into 4 parts: MBR, Application code, Configuration and System Info area.

• MBR Area: It is known as Main Boot Record. Occupy 12KB flash space from address 0KB to 12KB.
• System Info Area: Save some system info. It occupies 4KB flash spacef from address 12KB to 16KB
• Application Code Area: Save the user application code, its size depend on user's design.
• Configuration Area: It is used to save some config data, such as bluetooth address, device name, some user config, and so on.

User can use the free area to save the custom data.

OM6XXX Flash Layout

Note

If the chip supports Secure Boot, please look at its flash layout.

External SPI Flash

OM6XXX supports external SPI Flash, its cachable address is also located at [0x00400000,0x00800000), and non-cachable address is in [0x50000000,0x51000000). Its pin defined like follow:

External SPI Flash Pin Configurations

Pin Descriptions:

No.	Symbol	Extension	Remarks
1	CS#	-	Chip select
2	SO	SIO1	Serial data output for 1 x I/O, Serial data input and output for 4 x I/O read mode
3	WP#	SIO2	Write protection active low, Serial data input and output for 4 x I/O read mode
4	GND	-	Ground of the device
5	SI	SIO0	Serial data input for 1x I/O, Serial data input and output for 4 x I/O read mode
6	SCLK	-	Serial interface clock input
7	HOLD#	SIO3	To pause the device without deselecting the device, Serial data input and output for 4 x I/O read mode
8	VCC	-	Power supply of the device

Flash API

• Read

  void drv_sf_read(HS_SF_Type *sf, uint32_t cs, uint32_t addr, void *data, uint32_t length);

• Write

  void drv_sf_write(HS_SF_Type *sf, uint32_t cs, uint32_t addr, const void *data, uint32_t length);

• Erase

  void drv_sf_erase(HS_SF_Type *sf, uint32_t cs, uint32_t addr, uint32_t length);

API reference: drv_sf.h

Bit Modes

Except to the standard Serial Peripheral Interface (SPI), most flash models also support high performance Dual/Quad modes I/O SPI controlled by six pins :

• Serial Clock (CLK)
• Chip Select (CS#)
• Serial Data I/O0 (DI)
• Serial Data I/O1 (DO)
• Serial Data IO2 (WP#)
• Serial Data I/O3 (HOLD#)

Three Bit Modes

1. Single Mode Standard SPI mode as called 1 bit-mode, which only use CLK, CS#, DI, and DO. WP# is still available for Write Protect Input, and HOLD# is also available for Hold Input.
2. Dual Mode as called 2-bit mode, uses CLK, CS#, and also uses DI as IO0, DO as IO1. The same with Single mode, WP# and HOLD# are also available.
3. Quad mode as called 4-bit mode, needs six pins, uses CLK, CS#, and also uses DI as IO0, DO as IO1, WP# as IO2, and HOLD# as IO3. Since all pins are used, Write Protect and Hold functions do not work in Quad mode.

Although almost all flash models support Dual and Quad modes, the command set and mode switch rules are not all same.

Bit Mode Switch

In order to support as many flash models as possible, single mode (1 bit-mode) is used at boot time. If users need to switch to high speed bit mode (2 or 4 bit mode), the interface provided in the SDK is called: drv_sf_config() to switch to high bit mode. The parameter "width" is used to configure bit mode, and return value of the function indicates whether the switch is successful.

The prototype of the interface function provided by SDK for bit mode switching is as follows:

void drv_sf_config(HS_SF_Type *sf, uint32_t cs, const drv_sf_config_t *config)

Software Block Protect

Although flash supports HW protect pin (WP#) to lock all flash to prevent writing and erasing operations, there are still two disadvantages.

1. If WP# is used for flash protection, Quad mode (4-bit mode) is not allowed.
2. HW protection can just choose to protect all or protect none, can’t protect partially.

A mechanism to solve these problems is flash software Blocks Protection (BPx). It uses some BP bits in flash status register to select the level (range) to protect.

The following table is the status register bitmap :

Bit	S15	S14	S13	S12	S11	S10	S9	S8	S7	S6	S5	S4	S3	S2	S1	S0
Define	SUS1	CMP	LB3	LB2	LB1	SUS2	QE	SRP1	SRP0	BP4	BP3	BP2	BP1	BP0	WEL	WIP

The definition of the status register bits is as below :

WIP bit
The Write in Progress(WIP)bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1,means it is busy,otherwise not.

WEL bit
The Write Enable Latch(WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,Program or Erase command is accepted.

BP0 BP1 BP2 BP3 BP4 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands.These bits are written with the Write Status Register(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table “Protected Area Sizes”).becomes protected against Page Program (PP), Page Erase (PE), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP4, BP3, BP2, BP1and BP0) are set to “None protected”.

SRP0 SRP1 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection.

SRP1	SRP0	#WP	Status Register	Description
0	0	X	Software Protected	The Status Register can be written to after a Write Enable command, WEL=1.(Default)
0	1	0	Hardware Protected	WP#=0, the Status Register locked and cannot be written to.

QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).

LB3 LB2 LB1 bits
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1are0, the security registers are unlocked. The LB3-LB1bitscan be set to 1 individually using the Write Register instruction. The LB3-LB1bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently.

CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details. The default setting is CMP=0.

SUS1 SUS2 bits
The SUS1 and SUS2bit are read only bit in the status register (S15and S10) that are set to 1 after interrupting an program/erase/write status register progress by Program/Erase Suspend (75H or B0H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH or 30H) command as well as a power-down, power-up cycle.

The following tables shows the Protected Area Sizes of (4Mb and 8Mb Flash), setting by CMP and BPx bits :

• Flash Size : 4Mb, CMP=0.

BP4	BP3	BP2	BP1	BP0	Blocks	Addresses	Density
x	x	0	0	0	None	None	None
0	0	0	0	1	7	0x070000 - 0x07FFFF	64KB
0	0	0	1	0	6 and 7	0x060000 - 0x07FFFF	128KB
0	0	0	1	1	4 to 7	0x040000 - 0x07FFFF	256KB
0	1	0	0	1	0	0x000000 - 0x00FFFF	64KB
0	1	0	1	0	0 and 1	0x000000 - 0x01FFFF	128KB
0	1	0	1	1	0 to 3	0x000000 - 0x03FFFF	256KB
0	x	1	x	x	0 to 7	0x000000 - 0x07FFFF	512KB(ALL)
1	0	0	0	1	7	0x07F000 - 0x07FFFF	4KB
1	0	0	1	0	7	0x07E000 - 0x07FFFF	8KB
1	0	0	1	1	7	0x07C000 - 0x07FFFF	16KB
1	0	1	0	x	7	0x078000 - 0x07FFFF	32KB
1	0	1	1	0	7	0x078000 - 0x07FFFF	32KB
1	1	0	0	1	0	0x000000 - 0x00FFFF	4KB
1	1	0	1	0	0	0x000000 - 0x001FFF	8KB
1	1	0	1	1	0	0x000000 - 0x003FFF	16KB
1	1	1	0	x	0	0x000000 - 0x007FFF	32KB
1	1	1	1	0	0	0x000000 - 0x007FFF	32KB
1	x	1	1	1	0 to 7	0x000000 - 0x07FFFF	512KB(ALL)

• Flash Size : 4Mb, CMP=1.

BP4	BP3	BP2	BP1	BP0	Blocks	Addresses	Density
x	x	0	0	0	0 to 7	0x000000 - 0x07FFFF	512KB(ALL)
0	0	0	0	1	0 to 6	0x000000 - 0x06FFFF	448KB
0	0	0	1	0	0 to 5	0x000000 - 0x05FFFF	384KB
0	0	0	1	1	0 to 3	0x000000 - 0x03FFFF	256KB
0	1	0	0	1	1 to 7	0x010000 - 0x07FFFF	448KB
0	1	0	1	0	2 to 7	0x020000 - 0x07FFFF	384KB
0	1	0	1	1	4 to 7	0x040000 - 0x07FFFF	256KB
0	x	1	x	x	None	None	None
1	0	0	0	1	0 to 7	0x000000 - 0x07EFFF	508KB
1	0	0	1	0	0 to 7	0x000000 - 0x07DFFF	504KB
1	0	0	1	1	0 to 7	0x000000 - 0x07BFFF	496KB
1	0	1	0	x	0 to 7	0x000000 - 0x077FFF	480KB
1	0	1	1	0	0 to 7	0x000000 - 0x077FFF	480KB
1	1	0	0	1	0 to 7	0x001000 - 0x07FFFF	508KB
1	1	0	1	0	0 to 7	0x002000 - 0x07FFFF	504KB
1	1	0	1	1	0 to 7	0x004000 - 0x07FFFF	496KB
1	1	1	0	x	0 to 7	0x008000 - 0x07FFFF	480KB
1	1	1	1	0	0 to 7	0x008000 - 0x07FFFF	480KB
1	x	1	1	1	None	None	None

• Flash Size : 8Mb, CMP=0.

BP4	BP3	BP2	BP1	BP0	Blocks	Addresses	Density
x	x	0	0	0	None	None	None
0	0	0	0	1	15	0x0F0000 - 0x0FFFFF	64KB
0	0	0	1	0	14 and 15	0x0E0000 - 0x0FFFFF	128KB
0	0	0	1	1	12 to 15	0x0C0000 - 0x0FFFFF	256KB
0	0	1	0	0	8 to 15	0x080000 - 0x0FFFFF	512KB
0	1	0	0	1	0	0x000000 - 0x00FFFF	64KB
0	1	0	1	0	0 and 1	0x000000 - 0x01FFFF	128KB
0	1	0	1	1	0 to 3	0x000000 - 0x03FFFF	256KB
0	1	1	0	0	0 to 7	0x000000 - 0x07FFFF	512KB
0	x	1	0	1	0 to 15	0x000000 - 0x0FFFFF	1MB(ALL)
x	x	1	1	x	0 to 15	0x000000 - 0x0FFFFF	1MB(ALL)
1	0	0	0	1	15	0x0FF000 - 0x0FFFFF	4KB
1	0	0	1	0	15	0x0FE000 - 0x0FFFFF	8KB
1	0	0	1	1	15	0x0FC000 - 0x0FFFFF	16KB
1	0	1	0	x	15	0x0F8000 - 0x0FFFFF	32KB
1	1	0	0	1	0	0x000000 - 0x00FFFF	4KB
1	1	0	1	0	0	0x000000 - 0x001FFF	8KB
1	1	0	1	1	0	0x000000 - 0x003FFF	16KB
1	1	1	0	x	0	0x000000 - 0x007FFF	32KB

• Flash Size : 8Mb, CMP=1.

BP4	BP3	BP2	BP1	BP0	Blocks	Addresses	Density
x	x	0	0	0	0 to 15	0x000000 - 0x0FFFFF	1MB(ALL)
0	0	0	0	1	0 to 14	0x000000 - 0x0EFFFF	960KB
0	0	0	1	0	0 to 13	0x000000 - 0x0DFFFF	896KB
0	0	0	1	1	0 to 11	0x000000 - 0x0BFFFF	768KB
0	0	1	0	0	0 to 7	0x000000 - 0x07FFFF	512KB
0	1	0	0	1	1 to 15	0x010000 - 0x0FFFFF	960KB
0	1	0	1	0	2 to 15	0x020000 - 0x0FFFFF	896KB
0	1	0	1	1	4 to 15	0x040000 - 0x0FFFFF	768KB
0	1	1	0	0	8 to 15	0x080000 - 0x0FFFFF	512KB
0	x	1	0	1	None	None	None
x	x	1	1	x	None	None	None
1	0	0	0	1	0 to 15	0x000000 - 0x0FEFFF	1020KB
1	0	0	1	0	0 to 15	0x000000 - 0x0FDFFF	1016KB
1	0	0	1	1	0 to 15	0x000000 - 0x0FBFFF	1008KB
1	0	1	0	x	0 to 15	0x000000 - 0x0F7FFF	992KB
1	1	0	0	1	0 to 15	0x001000 - 0x0FFFFF	1020KB
1	1	0	1	0	0 to 15	0x002000 - 0x0FFFFF	1016KB
1	1	0	1	1	0 to 15	0x004000 - 0x0FFFFF	1008KB
1	1	1	0	x	0 to 15	0x008000 - 0x0FFFFF	992KB

Flash Status Register Read and Write API

• Read

  // Return status register value
  uint16_t drv_sf_read_sr_16bits(OM_SF_Type *sf, uint32_t cs);

• Write

  // Put status register value
  void drv_sf_write_sr_16bits(OM_SF_Type *sf, uint32_t cs, uint16_t sr);

Power Mode

The power mode of Flash is mainly divided into three scenarios: working, standby and Power Down. The power consumption of the working mode is generally about 10 mA, while the power consumption of standby mode is usually about 10uA order of magnitude. The power consumption of the Power Down mode is lower, even less than 1 uA.

Flash automatically enters the standby mode without any access, and automatically enters the working state when it needs to be accessed again.

After calling drv_sf_enable(), the flash will be power on. 1 second after calling the drv_sf_enable function, the flash will automatically power off. So just call drv_sf_enable function before operating flash.

Note

Unlike SRAM, flash is a non-volatile second storage. Because of 100K times program / erase limitation, flash is not suggested for performing write/erase operations frequently.

XIP

If the remaining RAM space is enough, APP code can be directly executed on RAM, which is conducive to improving performance and reducing power consumption. However, if the APP code is so large that the remaining RAM space is not enough, some or all of the APP codes need to be executed on flash.

All demos in projects directory are XIP mode.