971 lines
34 KiB
C
971 lines
34 KiB
C
/**
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*********************************************************************************************************
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* Copyright(c) 2019, Realtek Semiconductor Corporation. All rights reserved.
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*********************************************************************************************************
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* \file rtl876x_gdma.h
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* \brief The header file of the peripheral GDMA driver.
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* \details This file provides all GDMA firmware functions.
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* \author yuan
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* \date 2019-11-14
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* \version v1.0
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* *********************************************************************************************************
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*/
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#ifndef _RTL876X_GDMA_H_
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#define _RTL876X_GDMA_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \addtogroup IO Peripheral Drivers
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* \defgroup GDMA GDMA
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*
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* \brief Manage the GDMA peripheral functions.
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*
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* \ingroup IO
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*/
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/*============================================================================*
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* Includes
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*============================================================================*/
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#include "rtl876x.h"
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/*============================================================================*
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* Types
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*============================================================================*/
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/**
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* \defgroup GDMA_Exported_Types Init Params Struct
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*
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* \ingroup GDMA
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*/
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/**
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* \brief GDMA init structure definition.
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*
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* \ingroup GDMA_Exported_Types
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*/
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typedef struct
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{
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uint8_t GDMA_ChannelNum; /*!< Specifies channel number for GDMA. */
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uint8_t GDMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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This parameter can be a value of \ref GDMA_Data_Transfer_Direction. */
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uint32_t GDMA_BufferSize; /*!< Specifies the buffer size(<=4095), in data unit, of the specified Channel.
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The data unit is equal to the configuration set in DMA_PeripheralDataSize
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or DMA_MemoryDataSize members depending in the transfer direction. */
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uint8_t GDMA_SourceInc; /*!< Specifies whether the source address register is incremented or not.
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This parameter can be a value of \ref GDMA_Source_Incremented_Mode */
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uint8_t GDMA_DestinationInc; /*!< Specifies whether the destination address register is incremented or not.
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This parameter can be a value of \ref GDMA_Destination_Incremented_Mode. */
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uint32_t GDMA_SourceDataSize; /*!< Specifies the source data width.
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This parameter can be a value of \ref GDMA_Data_Size */
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uint32_t GDMA_DestinationDataSize; /*!< Specifies the Memory data width.
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This parameter can be a value of \ref GDMA_Data_Size */
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uint32_t GDMA_SourceMsize; /*!< Specifies the number of data items to be transferred.
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This parameter can be a value of \ref GDMA_Msize */
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uint32_t GDMA_DestinationMsize; /*!< Specifies the number of data items to be transferred.
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This parameter can be a value of \ref GDMA_Msize */
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uint32_t GDMA_SourceAddr; /*!< Specifies the source base address for GDMA Channelx. */
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uint32_t GDMA_DestinationAddr; /*!< Specifies the destination base address for GDMA Channelx. */
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uint32_t GDMA_ChannelPriority; /*!< Specifies the software priority for the GDMA Channelx. */
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uint32_t GDMA_Multi_Block_Mode; /*!< Specifies the multi block transfer mode.
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This parameter can be a value of \ref GDMA_Multiblock_Mode. */
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uint32_t GDMA_Multi_Block_Struct; /*!< Pointer to the first struct of LLI. */
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uint8_t GDMA_Multi_Block_En; /*!< Enable or disable multi-block function. */
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uint8_t GDMA_SourceHandshake; /*!< Specifies the handshake index in source.
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This parameter can be a value of \ref GDMA_Handshake_Type. */
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uint8_t GDMA_DestHandshake; /*!< Specifies the handshake index in Destination.
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This parameter can be a value of \ref GDMA_Handshake_Type. */
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} GDMA_InitTypeDef;
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/**
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* \brief GDMA link list item structure definition.
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*
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* \ingroup GDMA_Exported_Types
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*/
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typedef struct
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{
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__IO uint32_t SAR;
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__IO uint32_t DAR;
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__IO uint32_t LLP;
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__IO uint32_t CTL_LOW;
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__IO uint32_t CTL_HIGH;
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} GDMA_LLIDef;
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#define DMA_CH_BASE(ChNum) ((GDMA_ChannelTypeDef *) (GDMA_CHANNEL_REG_BASE + ChNum * 0x0058))
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/*============================================================================*
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* Constants
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*============================================================================*/
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/**
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* \defgroup GDMA_Exported_Constants Macro Definitions
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*
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* \ingroup GDMA
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*/
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#define IS_GDMA_ALL_PERIPH(PERIPH) (((PERIPH) == GDMA_Channel0) || \
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((PERIPH) == GDMA_Channel1) || \
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((PERIPH) == GDMA_Channel2) || \
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((PERIPH) == GDMA_Channel3))
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#define IS_GDMA_ChannelNum(NUM) ((NUM) < 4)
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/**
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* \defgroup GDMA_Handshake_Type GDMA Handshake Type
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define GDMA_Handshake_UART0_TX (0)
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#define GDMA_Handshake_UART0_RX (1)
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#define GDMA_Handshake_ENH_TIM0 (2)
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#define GDMA_Handshake_ENH_TIM1 (3)
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#define GDMA_Handshake_SPI0_TX (4)
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#define GDMA_Handshake_SPI0_RX (5)
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#define GDMA_Handshake_SPI1_TX (6)
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#define GDMA_Handshake_SPI1_RX (7)
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#define GDMA_Handshake_I2C0_TX (8)
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#define GDMA_Handshake_I2C0_RX (9)
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#define GDMA_Handshake_I2C1_TX (10)
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#define GDMA_Handshake_I2C1_RX (11)
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#define GDMA_Handshake_ADC (12)
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#define GDMA_Handshake_AES_TX (13)
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#define GDMA_Handshake_AES_RX (14)
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#define GDMA_Handshake_UART1_TX (15)
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#define GDMA_Handshake_I2S0_TX (16)
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#define GDMA_Handshake_I2S0_RX (17)
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#define GDMA_Handshake_SPIC0_TX (20)
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#define GDMA_Handshake_SPIC0_RX (21)
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#define GDMA_Handshake_UART1_RX (23)
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#define GDMA_Handshake_TIM0 (24)
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#define GDMA_Handshake_TIM1 (25)
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#define GDMA_Handshake_TIM2 (26)
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#define GDMA_Handshake_IR_TX (27)
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#define GDMA_Handshake_IR_RX (28)
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#define GDMA_Handshake_TIM3 (29)
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#define GDMA_Handshake_TIM4 (30)
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#define GDMA_Handshake_TIM5 (31)
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/** \} */
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#define IS_GDMA_TransferType(Type) (((Type) == GDMA_Handshake_UART0_TX) || \
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((Type) == GDMA_Handshake_UART0_RX) || \
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((Type) == GDMA_Handshake_ENH_TIM0) || \
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((Type) == GDMA_Handshake_ENH_TIM1) || \
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((Type) == GDMA_Handshake_SPI0_TX) || \
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((Type) == GDMA_Handshake_SPI0_RX) || \
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((Type) == GDMA_Handshake_SPI1_TX) || \
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((Type) == GDMA_Handshake_SPI1_RX) || \
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((Type) == GDMA_Handshake_I2C0_TX) || \
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((Type) == GDMA_Handshake_I2C0_RX) || \
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((Type) == GDMA_Handshake_I2C1_TX) || \
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((Type) == GDMA_Handshake_I2C1_RX) || \
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((Type) == GDMA_Handshake_ADC) || \
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((Type) == GDMA_Handshake_AES_TX) || \
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((Type) == GDMA_Handshake_AES_RX) || \
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((Type) == GDMA_Handshake_UART1_TX) || \
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((Type) == GDMA_Handshake_I2S0_TX) || \
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((Type) == GDMA_Handshake_I2S0_RX) || \
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((Type) == GDMA_Handshake_SPIC0_TX) || \
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((Type) == GDMA_Handshake_SPIC0_RX) ||\
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((Type) == GDMA_Handshake_UART1_RX) || \
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((Type) == GDMA_Handshake_IR_TX) ||\
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((Type) == GDMA_Handshake_IR_RX) ||\
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((Type) == GDMA_Handshake_TIM0) ||\
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((Type) == GDMA_Handshake_TIM1) ||\
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((Type) == GDMA_Handshake_TIM2) ||\
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((Type) == GDMA_Handshake_TIM3) ||\
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((Type) == GDMA_Handshake_TIM4) ||\
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((Type) == GDMA_Handshake_TIM5))
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/**
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* \defgroup GDMA_Data_Size GDMA Data Size
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define GDMA_DataSize_Byte ((uint32_t)0x00000000)
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#define GDMA_DataSize_HalfWord ((uint32_t)0x00000001)
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#define GDMA_DataSize_Word ((uint32_t)0x00000002)
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/** \} */
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#define IS_GDMA_DATA_SIZE(SIZE) (((SIZE) == GDMA_DataSize_Byte) || \
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((SIZE) == GDMA_DataSize_HalfWord) || \
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((SIZE) == GDMA_DataSize_Word))
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/**
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* \defgroup GDMA_Msize GDMA Msize
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define GDMA_Msize_1 ((uint32_t)0x00000000)
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#define GDMA_Msize_4 ((uint32_t)0x00000001)
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#define GDMA_Msize_8 ((uint32_t)0x00000002)
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#define GDMA_Msize_16 ((uint32_t)0x00000003)
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#define GDMA_Msize_32 ((uint32_t)0x00000004)
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#define GDMA_Msize_64 ((uint32_t)0x00000005)
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#define GDMA_Msize_128 ((uint32_t)0x00000006)
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#define GDMA_Msize_256 ((uint32_t)0x00000007)
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/** \} */
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#define IS_GDMA_MSIZE(SIZE) (((SIZE) == GDMA_Msize_1) || \
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((SIZE) == GDMA_Msize_4) || \
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((SIZE) == GDMA_Msize_8) || \
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((SIZE) == GDMA_Msize_16) || \
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((SIZE) == GDMA_Msize_32) || \
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((SIZE) == GDMA_Msize_64) || \
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((SIZE) == GDMA_Msize_128) || \
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((SIZE) == GDMA_Msize_256))
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/**
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* \defgroup GDMA_Data_Transfer_Direction GDMA Data Transfer Direction
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define GDMA_DIR_MemoryToMemory ((uint32_t)0x00000000)
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#define GDMA_DIR_MemoryToPeripheral ((uint32_t)0x00000001)
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#define GDMA_DIR_PeripheralToMemory ((uint32_t)0x00000002)
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#define GDMA_DIR_PeripheralToPeripheral ((uint32_t)0x00000003)
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/** \} */
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#define IS_GDMA_DIR(DIR) (((DIR) == GDMA_DIR_MemoryToMemory) || \
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((DIR) == GDMA_DIR_MemoryToPeripheral) || \
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((DIR) == GDMA_DIR_PeripheralToMemory) ||\
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((DIR) == GDMA_DIR_PeripheralToPeripheral))
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/**
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* \defgroup GDMA_Source_Incremented_Mode GDMA Source Incremented Mode
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define DMA_SourceInc_Inc ((uint32_t)0x00000000)
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#define DMA_SourceInc_Dec ((uint32_t)0x00000001)
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#define DMA_SourceInc_Fix ((uint32_t)0x00000002)
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/** \} */
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#define IS_GDMA_SourceInc(STATE) (((STATE) == DMA_SourceInc_Inc) || \
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((STATE) == DMA_SourceInc_Dec) || \
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((STATE) == DMA_SourceInc_Fix))
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/**
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* \defgroup GDMA_Destination_Incremented_Mode GDMA Destination Incremented Mode
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define DMA_DestinationInc_Inc ((uint32_t)0x00000000)
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#define DMA_DestinationInc_Dec ((uint32_t)0x00000001)
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#define DMA_DestinationInc_Fix ((uint32_t)0x00000002)
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/** \} */
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#define IS_GDMA_DestinationInc(STATE) (((STATE) == DMA_DestinationInc_Inc) || \
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((STATE) == DMA_DestinationInc_Dec) || \
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((STATE) == DMA_DestinationInc_Fix))
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/**
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* \defgroup DMA_Interrupts_Definition DMA Interrupts Definition
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define GDMA_INT_Transfer ((uint32_t)0x00000001)
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#define GDMA_INT_Block ((uint32_t)0x00000002)
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#define GDMA_INT_SrcTransfer ((uint32_t)0x00000004)
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#define GDMA_INT_DstTransfer ((uint32_t)0x00000008)
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#define GDMA_INT_Error ((uint32_t)0x00000010)
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/** \} */
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#define IS_GDMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFE00) == 0x00) && ((IT) != 0x00))
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/**
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* \defgroup GDMA_Multiblock_Mode GDMA Multi-block Mode
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* \{
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* \ingroup GDMA_Exported_Constants
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*/
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#define AUTO_RELOAD_WITH_CONTIGUOUS_SAR (BIT31)
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#define AUTO_RELOAD_WITH_CONTIGUOUS_DAR (BIT30)
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#define AUTO_RELOAD_TRANSFER (BIT30 | BIT31)
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#define LLI_WITH_CONTIGUOUS_SAR (BIT27)
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#define LLI_WITH_AUTO_RELOAD_SAR (BIT27 | BIT30)
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#define LLI_WITH_CONTIGUOUS_DAR (BIT28)
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#define LLI_WITH_AUTO_RELOAD_DAR (BIT28 | BIT31)
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#define LLI_TRANSFER (BIT27 | BIT28)
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/** \} */
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#define IS_GDMA_MULTIBLOCKMODE(MODE) (((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_SAR) || ((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_DAR)\
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||((MODE) == AUTO_RELOAD_TRANSFER) || ((MODE) == LLI_WITH_CONTIGUOUS_SAR)\
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||((MODE) == LLI_WITH_AUTO_RELOAD_SAR) || ((MODE) == LLI_WITH_CONTIGUOUS_DAR)\
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||((MODE) == LLI_WITH_AUTO_RELOAD_DAR) || ((MODE) == LLI_TRANSFER))
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/**
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* \def GDMA_Multiblock_Select_Bit Multi-Block Select Bit
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*
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*/
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#define AUTO_RELOAD_SELECTED_BIT (uint32_t)(0xC0000000)
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#define LLP_SELECTED_BIT (uint32_t)(0x18000000)
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/**
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* \def DMA_Suspend_Flag_Definition DMA Suspend Flag Definition
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*/
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#define GDMA_FIFO_STATUS (BIT(9))
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#define GDMA_SUSPEND_TRANSMISSSION (BIT(8))
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#define GDMA_SUSPEND_CMD_STATUS (BIT(2) | BIT(1))
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#define GDMA_SUSPEND_CHANNEL_STATUS (BIT(0))
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/*============================================================================*
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* Functions
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*============================================================================*/
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/**
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* \defgroup GDMA_Exported_Functions Peripheral APIs
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* \{
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* \ingroup GDMA
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*/
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/**
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* \brief Deinitializes the GDMA registers to their default reset
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* values.
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* \param None.
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* \return None.
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*
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* <b>Example usage</b>
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* \code{.c}
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*
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* void driver_gdma_init(void)
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* {
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* GDMA_DeInit();
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* }
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* \endcode
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*/
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void GDMA_DeInit(void);
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/**
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* \brief Initializes the GDMA Channelx according to the specified
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* parameters in the GDMA_InitStruct.
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* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the DMA Channel.
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* \param[in] GDMA_InitStruct: Pointer to a GDMA_InitTypeDef structure that
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* contains the configuration information for the specified DMA Channel.
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* \return None.
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*
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* <b>Example usage</b>
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* \code{.c}
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*
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* void driver_gdma_init(void)
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* {
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*
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* for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
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* {
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* GDMA_SendData_Buffer[i] = 0x10 + i;
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* }
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* GDMA_InitTypeDef GDMA_InitStruct;
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* GDMA_StructInit(&GDMA_InitStruct);
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* GDMA_InitStruct.GDMA_ChannelNum = 1;
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* GDMA_InitStruct.GDMA_DIR = GDMA_DIR_MemoryToPeripheral;
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* GDMA_InitStruct.GDMA_BufferSize = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
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* GDMA_InitStruct.GDMA_SourceInc = DMA_SourceInc_Inc;
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* GDMA_InitStruct.GDMA_DestinationInc = DMA_DestinationInc_Fix;
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* GDMA_InitStruct.GDMA_SourceDataSize = GDMA_DataSize_Byte;
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* GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
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* GDMA_InitStruct.GDMA_SourceMsize = GDMA_Msize_1;
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* GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
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* GDMA_InitStruct.GDMA_SourceAddr = (uint32_t)GDMA_SendData_Buffer;
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* GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
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* GDMA_InitStruct.GDMA_DestHandshake = GDMA_Handshake_UART0_TX;
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* GDMA_InitStruct.GDMA_ChannelPriority = 2;//channel prority between 0 to 5
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* GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
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* GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
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* NVIC_InitTypeDef NVIC_InitStruct;
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* NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
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* NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
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* NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
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* NVIC_Init(&NVIC_InitStruct);
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* GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
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* }
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* \endcode
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*/
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void GDMA_Init(GDMA_ChannelTypeDef *GDMA_Channelx, GDMA_InitTypeDef *GDMA_InitStruct);
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/**
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* \brief Fills each GDMA_InitStruct member with its default value.
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* \param[in] GDMA_InitStruct : pointer to a GDMA_InitTypeDef structure which will
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* be initialized.
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* \return None.
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*
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* <b>Example usage</b>
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* \code{.c}
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*
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* void driver_gdma_init(void)
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* {
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*
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* for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
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* {
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* GDMA_SendData_Buffer[i] = 0x10 + i;
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* }
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* GDMA_InitTypeDef GDMA_InitStruct;
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* GDMA_StructInit(&GDMA_InitStruct);
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* GDMA_InitStruct.GDMA_ChannelNum = 1;
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* GDMA_InitStruct.GDMA_DIR = GDMA_DIR_MemoryToPeripheral;
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* GDMA_InitStruct.GDMA_BufferSize = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
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* GDMA_InitStruct.GDMA_SourceInc = DMA_SourceInc_Inc;
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* GDMA_InitStruct.GDMA_DestinationInc = DMA_DestinationInc_Fix;
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* GDMA_InitStruct.GDMA_SourceDataSize = GDMA_DataSize_Byte;
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* GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
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* GDMA_InitStruct.GDMA_SourceMsize = GDMA_Msize_1;
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* GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
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* GDMA_InitStruct.GDMA_SourceAddr = (uint32_t)GDMA_SendData_Buffer;
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* GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
|
|
* GDMA_InitStruct.GDMA_DestHandshake = GDMA_Handshake_UART0_TX;
|
|
* GDMA_InitStruct.GDMA_ChannelPriority = 2;//channel prority between 0 to 5
|
|
* GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
|
|
*
|
|
* }
|
|
* \endcode
|
|
*/
|
|
void GDMA_StructInit(GDMA_InitTypeDef *GDMA_InitStruct);
|
|
|
|
/**
|
|
* \brief Enables or disables the selected GDMA channel.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \param[in] NewState: New state of the selected DMA channel.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void driver_gdma_init(void)
|
|
* {
|
|
*
|
|
* for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
|
|
* {
|
|
* GDMA_SendData_Buffer[i] = 0x10 + i;
|
|
* }
|
|
|
|
* GDMA_InitTypeDef GDMA_InitStruct;
|
|
* GDMA_StructInit(&GDMA_InitStruct);
|
|
* GDMA_InitStruct.GDMA_ChannelNum = 1;
|
|
* GDMA_InitStruct.GDMA_DIR = GDMA_DIR_MemoryToPeripheral;
|
|
* GDMA_InitStruct.GDMA_BufferSize = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
|
|
* GDMA_InitStruct.GDMA_SourceInc = DMA_SourceInc_Inc;
|
|
* GDMA_InitStruct.GDMA_DestinationInc = DMA_DestinationInc_Fix;
|
|
* GDMA_InitStruct.GDMA_SourceDataSize = GDMA_DataSize_Byte;
|
|
* GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
|
|
* GDMA_InitStruct.GDMA_SourceMsize = GDMA_Msize_1;
|
|
* GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
|
|
* GDMA_InitStruct.GDMA_SourceAddr = (uint32_t)GDMA_SendData_Buffer;
|
|
* GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
|
|
* GDMA_InitStruct.GDMA_DestHandshake = GDMA_Handshake_UART0_TX;
|
|
* GDMA_InitStruct.GDMA_ChannelPriority = 2;//channel prority between 0 to 5
|
|
* GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
|
|
|
|
* GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
|
|
|
|
* NVIC_InitTypeDef NVIC_InitStruct;
|
|
* NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
|
|
* NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
|
|
* NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
|
|
* NVIC_Init(&NVIC_InitStruct);
|
|
|
|
* GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
void GDMA_Cmd(uint8_t GDMA_Channel_Num, FunctionalState NewState);
|
|
|
|
/**
|
|
* \brief Enables or disables the specified DMA channelx interrupt source.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \param[in] GDMA_IT: Specifies the GDMA interrupt source to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* \arg GDMA_INT_Transfer: Transfer complete interrupt source.
|
|
* \arg GDMA_INT_Block: Block transfer interrupt source.
|
|
* \arg GDMA_INT_SrcTransfer: SourceTransfer interrupt source.
|
|
* \arg GDMA_INT_DstTransfer: Destination Transfer interruptsource.
|
|
* \arg GDMA_INT_Error: Transfer error interrupt source.
|
|
* \param[in] NewState: New state of the specified DMA interrupt source.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void driver_gdma_init(void)
|
|
* {
|
|
*
|
|
* for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
|
|
* {
|
|
* GDMA_SendData_Buffer[i] = 0x10 + i;
|
|
* }
|
|
|
|
* GDMA_InitTypeDef GDMA_InitStruct;
|
|
* GDMA_StructInit(&GDMA_InitStruct);
|
|
* GDMA_InitStruct.GDMA_ChannelNum = 1;
|
|
* GDMA_InitStruct.GDMA_DIR = GDMA_DIR_MemoryToPeripheral;
|
|
* GDMA_InitStruct.GDMA_BufferSize = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
|
|
* GDMA_InitStruct.GDMA_SourceInc = DMA_SourceInc_Inc;
|
|
* GDMA_InitStruct.GDMA_DestinationInc = DMA_DestinationInc_Fix;
|
|
* GDMA_InitStruct.GDMA_SourceDataSize = GDMA_DataSize_Byte;
|
|
* GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
|
|
* GDMA_InitStruct.GDMA_SourceMsize = GDMA_Msize_1;
|
|
* GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
|
|
* GDMA_InitStruct.GDMA_SourceAddr = (uint32_t)GDMA_SendData_Buffer;
|
|
* GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
|
|
* GDMA_InitStruct.GDMA_DestHandshake = GDMA_Handshake_UART0_TX;
|
|
* GDMA_InitStruct.GDMA_ChannelPriority = 2;//channel prority between 0 to 5
|
|
* GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
|
|
|
|
* GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
|
|
|
|
* NVIC_InitTypeDef NVIC_InitStruct;
|
|
* NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
|
|
* NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
|
|
* NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
|
|
* NVIC_Init(&NVIC_InitStruct);
|
|
|
|
* GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
void GDMA_INTConfig(uint8_t GDMA_Channel_Num, uint32_t GDMA_IT, FunctionalState NewState);
|
|
|
|
/**
|
|
* \brief Clear the specified DMA channelx interrupt pending bit.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \param[in] GDMA_IT: Specifies the GDMA interrupts sources to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* \arg GDMA_INT_Transfer: Transfer complete interrupt source.
|
|
* \arg GDMA_INT_Block: Block transfer interrupt source.
|
|
* \arg GDMA_INT_SrcTransfer: SourceTransfer interrupt source.
|
|
* \arg GDMA_INT_DstTransfer: Destination Transfer interruptsource.
|
|
* \arg GDMA_INT_Error: Transfer error interrupt source.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* driver_gdma_init();
|
|
* }
|
|
*
|
|
* void UART_TX_GDMA_Handler(void)
|
|
* {
|
|
* GDMA_ClearINTPendingBit(1, GDMA_INT_Transfer);
|
|
* //Add user code here.
|
|
* }
|
|
* \endcode
|
|
*/
|
|
void GDMA_ClearINTPendingBit(uint8_t GDMA_Channel_Num, uint32_t GDMA_IT);
|
|
|
|
/**
|
|
* \brief Get selected GDMA channel status.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \return GDMA channel status.
|
|
* \retval SET: Channel is be used
|
|
* \retval RESET: Channel is free.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* FlagStatus flag_status = GDMA_GetChannelStatus(0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE FlagStatus GDMA_GetChannelStatus(uint8_t GDMA_Channel_Num)
|
|
{
|
|
FlagStatus bit_status = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
|
|
|
|
if ((GDMA_BASE->ChEnReg & BIT(GDMA_Channel_Num)) != (uint32_t)RESET)
|
|
{
|
|
|
|
bit_status = SET;
|
|
}
|
|
|
|
/* Return the selected channel status */
|
|
return bit_status;
|
|
}
|
|
|
|
/**
|
|
* \brief Check whether GDMA Channel transfer interrupt is set.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \return Transfer interrupt status, SET or RESET.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* ITStatus int_status = GDMA_GetTransferINTStatus(0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE ITStatus GDMA_GetTransferINTStatus(uint8_t GDMA_Channel_Num)
|
|
{
|
|
ITStatus bit_status = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
|
|
|
|
if ((GDMA_BASE->STATUS_TFR & BIT(GDMA_Channel_Num)) != (uint32_t)RESET)
|
|
{
|
|
|
|
bit_status = SET;
|
|
}
|
|
|
|
/* Return the transfer interrupt status */
|
|
return bit_status;
|
|
}
|
|
|
|
/**
|
|
* \brief Clear GDMA Channelx all interrupt.
|
|
* \param[in] GDMA_Channel_Num: GDMA channel number, can be 0~3.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* GDMA_ClearAllTypeINT(0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_ClearAllTypeINT(uint8_t GDMA_Channel_Num)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
|
|
|
|
GDMA_BASE->CLEAR_TFR = BIT(GDMA_Channel_Num);
|
|
GDMA_BASE->CLEAR_BLOCK = BIT(GDMA_Channel_Num);
|
|
GDMA_BASE->CLEAR_DST_TRAN = BIT(GDMA_Channel_Num);
|
|
GDMA_BASE->CLEAR_SRC_TRAN = BIT(GDMA_Channel_Num);
|
|
GDMA_BASE->CLEAR_ERR = BIT(GDMA_Channel_Num);
|
|
}
|
|
|
|
/**
|
|
* \brief Set GDMA transmission source address.
|
|
* \param[in] GDMA_Channelx: where x can be 0 to 3 to select the DMA Channel.
|
|
* \param[in] Address: Source address.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* uint32_t data_buf[10] = {0};
|
|
* GDMA_SetSourceAddress(GDMA_Channel0,(uint32_t)data_buf);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_SetSourceAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
GDMA_Channelx->SAR = Address;
|
|
}
|
|
|
|
/**
|
|
* \brief Set GDMA transmission destination address.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \param[in] Address: Destination address.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* uint32_t data_buf[10] = {0};
|
|
* GDMA_SetDestinationAddress(GDMA_Channel0,(uint32_t)data_buf);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_SetDestinationAddress(GDMA_ChannelTypeDef *GDMA_Channelx,
|
|
uint32_t Address)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
GDMA_Channelx->DAR = Address;
|
|
}
|
|
|
|
/**
|
|
* \brief Set GDMA buffer size.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \param[in] buffer_size: Set GDMA_BufferSize.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* uint32_t data_buf_size = 4095;//max
|
|
* GDMA_SetBufferSize(GDMA_Channel0,data_buf_size);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_SetBufferSize(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t buffer_size)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
/* configure high 32 bit of CTL register */
|
|
GDMA_Channelx->CTL_HIGH = buffer_size;
|
|
}
|
|
|
|
/**
|
|
* \brief Suspend GDMA transmission from the source.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \param[in] NewState: New state of the DMA Channelx.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* \return None.
|
|
* \note To prevent data loss, it is necessary to check whether FIFO data transmission is completed
|
|
* after suspend, and judge by checking whether GDMA FIFO is empty.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* GDMA_SuspendCmd(GDMA_Channel0,ENABLE);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_SuspendCmd(GDMA_ChannelTypeDef *GDMA_Channelx,
|
|
FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState == DISABLE)
|
|
{
|
|
/* Not suspend transmission*/
|
|
GDMA_Channelx->CFG_LOW &= ~(GDMA_SUSPEND_TRANSMISSSION);
|
|
}
|
|
else
|
|
{
|
|
/* Suspend transmission */
|
|
GDMA_Channelx->CFG_LOW |= GDMA_SUSPEND_TRANSMISSSION;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get GDMA transfer data length.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \return GDMA transfer data length.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* uint16_t data_len = GDMA_GetTransferLen(GDMA_Channel0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE uint16_t GDMA_GetTransferLen(GDMA_ChannelTypeDef *GDMA_Channelx)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
return (uint16_t)(GDMA_Channelx->CTL_HIGH & 0xffff);
|
|
}
|
|
|
|
/**
|
|
* \brief Set GDMA LLP stucture address.
|
|
* \param[in] GDMA_Channelx: Only for GDMA_Channel0~3.
|
|
* \param[in] Address: LLP stucture address.
|
|
* \return None.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* GDMA_LLIDef GDMA_LLIStruct[4000];
|
|
* GDMA_SetLLPAddress(GDMA_Channel0,(uint32_t)GDMA_LLIStruct);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE void GDMA_SetLLPAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
if ((GDMA_Channelx == GDMA_Channel0) | (GDMA_Channelx == GDMA_Channel1) | \
|
|
(GDMA_Channelx == GDMA_Channel2) | (GDMA_Channelx == GDMA_Channel3))
|
|
{
|
|
GDMA_Channelx->LLP = Address;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Check GDMA suspend channel status.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \return GDMA suspend channel status.
|
|
* \retval SET: Inactive.
|
|
* \retval RESET: Active.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* FlagStatus flag_status = GDMA_GetSuspendChannelStatus(GDMA_Channel0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE FlagStatus GDMA_GetSuspendChannelStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
|
|
{
|
|
FlagStatus bit_status = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
if ((GDMA_Channelx->CFG_LOW & GDMA_SUSPEND_CHANNEL_STATUS) == GDMA_SUSPEND_CHANNEL_STATUS)
|
|
{
|
|
bit_status = SET;
|
|
}
|
|
|
|
/* Return the selected channel suspend status */
|
|
return bit_status;
|
|
}
|
|
|
|
/**
|
|
* \brief Check GDMA suspend command status.
|
|
* \param GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \return GDMA suspend command status.
|
|
* \retval SET: Suspend.
|
|
* \retval RESET: Not suspend.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* FlagStatus flag_status = GDMA_GetSuspendCmdStatus(GDMA_Channel0);
|
|
* }
|
|
* \endcode
|
|
*/
|
|
__STATIC_INLINE FlagStatus GDMA_GetSuspendCmdStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
|
|
{
|
|
FlagStatus bit_status = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
|
|
|
|
if ((GDMA_Channelx->CFG_LOW & GDMA_SUSPEND_CMD_STATUS) == GDMA_SUSPEND_CMD_STATUS)
|
|
{
|
|
bit_status = SET;
|
|
}
|
|
|
|
/* Return the selected channel suspend status */
|
|
return bit_status;
|
|
}
|
|
|
|
/**
|
|
* \brief Check GDMA FIFO status.
|
|
* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
|
|
* \return GDMA FIFO status.
|
|
* \retval SET: FIFO empty.
|
|
* \retval RESET: FIFO not empty.
|
|
*
|
|
* <b>Example usage</b>
|
|
* \code{.c}
|
|
*
|
|
* void gdma_demo(void)
|
|
* {
|
|
* FlagStatus flag_status = GDMA_GetFIFOStatus(GDMA_Channel0);
|
|
* }
|
|
* \endcode
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*/
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__STATIC_INLINE FlagStatus GDMA_GetFIFOStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
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{
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FlagStatus bit_status = RESET;
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/* Check the parameters */
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assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
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if ((GDMA_Channelx->CFG_LOW & GDMA_FIFO_STATUS) != (uint32_t)RESET)
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{
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bit_status = SET;
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}
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/* Return the selected channel status */
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return bit_status;
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}
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/**
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* \brief Get GDMA source address.
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* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the DMA Channel.
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* \return Source address.
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*
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* <b>Example usage</b>
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* \code{.c}
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*
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* void gdma_demo(void)
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* {
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* uint32_t address = GDMA_GetSrcTransferAddress(GDMA_Channel0);
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* }
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* \endcode
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*/
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__STATIC_INLINE uint32_t GDMA_GetSrcTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
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{
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/* Check the parameters */
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assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
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|
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uint32_t address = 0;
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address = GDMA_Channelx->SAR;
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return address;
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}
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|
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/**
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* \brief Get GDMA destination address.
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* \param[in] GDMA_Channelx: Where x can be 0 to 3 to select the DMA Channel.
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* \return Destination address.
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|
*
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|
* <b>Example usage</b>
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|
* \code{.c}
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|
*
|
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* void gdma_demo(void)
|
|
* {
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* uint32_t address = GDMA_GetDstTransferAddress(GDMA_Channel0);
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* }
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* \endcode
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*/
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__STATIC_INLINE uint32_t GDMA_GetDstTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
|
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{
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/* Check the parameters */
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|
assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
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|
|
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uint32_t address = 0;
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address = GDMA_Channelx->DAR;
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return address;
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}
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/** \} */ /* End of group GDMA_Exported_Functions */
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#ifdef __cplusplus
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}
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#endif
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#endif /*_RTL8762X_GDMA_H_*/
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/******************* (C) COPYRIGHT 2019 Realtek Semiconductor Corporation *****END OF FILE****/
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