/**
*****************************************************************************************
* Copyright(c) 2020, Realtek Semiconductor Corporation. All rights reserved.
*****************************************************************************************
* @file rtl876x.h
* @brief CMSIS Cortex-M0+ Peripheral Access Layer Header File for
* RTL876X from Realtek Semiconductor.
* @date 2020.10.10
* @version v1.0
* @date 3. March 2015
*
* @note Generated with SVDConv Vx.xxp
* from CMSIS SVD File 'RTL876X.xml' Version x.xC,
*
* @par Copyright (c) 2020 Realtek Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Realtek Semiconductor.
* Terms and conditions of usage are described in detail in Realtek
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*
* *************************************************************************************
* @attention
* © COPYRIGHT 2020 Realtek Semiconductor Corporation
* *************************************************************************************
*/
#ifndef RTL876X_H
#define RTL876X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup RTL876X Rtl876x
* @brief CMSIS Cortex-M0+ peripheral access layer header file for
* RTL876X from Realtek Semiconductor
* @{
*/
/*============================================================================*
* Types
*============================================================================*/
/** @defgroup RTL876x_Exported_types RTL876X Exported types
* @{
*/
/** brief Interrupt Number Definition */
typedef enum IRQn
{
/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
System_IRQn = 0, /**< [0] System Interrupt */
WDG_IRQn, /**< [1] Watch Dog Interrupt */
BTMAC_IRQn, /**< [2] BTMAC Interrupt ( an Extension of interrupt ) */
Timer3_IRQn, /**< [3] Timer3 global interrupt */
Timer2_IRQn, /**< [4] Timer2 global interrupt */
Platform_IRQn, /**< [5] Platform error interrupt */
I2S0_RX_IRQn, /**< [6] I2S0 RX interrupt */
I2S0_TX_IRQn, /**< [7] I2S0 TX interrupt */
Timer4_5_IRQn, /**< [8] Timer 4 to 5 interrupt ( an Extension of interrupt ) */
GPIO4_IRQn, /**< [9] GPIO 4 interrupt */
GPIO5_IRQn, /**< [10] GPIO 5 interrupt */
UART1_IRQn, /**< [11] UART1 interrupt */
UART0_IRQn, /**< [12] UART0 interrupt */
RTC_IRQn, /**< [13] Realtime counter interrupt */
SPI0_IRQn, /**< [14] SPI0 interrupt */
SPI1_IRQn, /**< [15] SPI1 interrupt */
I2C0_IRQn, /**< [16] I2C0 interrupt */
I2C1_IRQn, /**< [17] I2C1 interrupt */
ADC_IRQn, /**< [18] ADC global interrupt */
Peripheral_IRQn, /**< [19] Peripheral Interrupt ( an Extension of interrupt ) */
GDMA0_Channel0_IRQn, /**< [20] RTK-DMA0 channel 0 global interrupt */
GDMA0_Channel1_IRQn, /**< [21] RTK-DMA0 channel 1 global interrupt */
GDMA0_Channel2_IRQn, /**< [22] RTK-DMA0 channel 2 global interrupt */
GDMA0_Channel3_IRQn, /**< [23] RTK-DMA0 channel 3 global interrupt */
ENHANCED_TIMER0_IRQn, /**< [24] Enhanced timer0 interrupt */
ENHANCED_TIMER1_IRQn, /**< [25] Enhanced timer1 interrupt */
GPIO_Group3_IRQn, /**< [26] GPIO Group3 Interrupt ( an Extension of interrupt ) */
GPIO_Group2_IRQn, /**< [27] GPIO Group2 Interrupt ( an Extension of interrupt ) */
IR_IRQn, /**< [28] IR Interrupt */
GPIO_Group1_IRQn, /**< [29] GPIO Group1 Interrupt ( an Extension of interrupt ) */
GPIO_Group0_IRQn, /**< [30] GPIO Group0 Interrupt ( an Extension of interrupt ) */
Reserved_IRQn, /**< [31] Reserved */
/****** Bee3 Extension Interrupt Numbers ************/
TIMER4_IRQ = 8,
TIMER5_IRQ = 8,
GPIO3_IRQn = 26,
GPIO7_IRQn = 26,
GPIO11_IRQn = 26,
GPIO15_IRQn = 26,
GPIO19_IRQn = 26,
GPIO23_IRQn = 26,
GPIO27_IRQn = 26,
GPIO31_IRQn = 26,
GPIO2_IRQn = 27,
GPIO6_IRQn = 27,
GPIO10_IRQn = 27,
GPIO14_IRQn = 27,
GPIO18_IRQn = 27,
GPIO22_IRQn = 27,
GPIO26_IRQn = 27,
GPIO30_IRQn = 27,
GPIO1_IRQn = 29,
GPIO9_IRQn = 29,
GPIO13_IRQn = 29,
GPIO17_IRQn = 29,
GPIO21_IRQn = 29,
GPIO25_IRQn = 29,
GPIO29_IRQn = 29,
GPIO0_IRQn = 30,
GPIO8_IRQn = 30,
GPIO12_IRQn = 30,
GPIO16_IRQn = 30,
GPIO20_IRQn = 30,
GPIO24_IRQn = 30,
GPIO28_IRQn = 30,
Peripheral_First_IRQn = 50,
SPIC0_IRQn = 50,
qdecode_IRQn = 51,
KeyScan_IRQn = 52,
SPI2W_IRQn = 53,
LPCOMP_IRQn = 54,
PTA_Mailbox_IRQn = 55,
CAP_TOUCH_IRQn = 56,
TRNG_IRQn = 57,
} IRQn_Type, *PIRQn_Type;
/** @} */ /* End of group RTL876x_Exported_types */
/** @defgroup Configuration_of_CMSIS Configuration of CMSIS
* @brief Configuration of the cm4 Processor and Core Peripherals
* @{
*/
/* ----------------Configuration of the cm0+ Processor and Core Peripherals---------------- */
#define __FPU_PRESENT 0 /* FPU present */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
/*============================================================================*
* Header Files
*============================================================================*/
/* Processor and core peripherals */
#include "core_cm0plus.h"
#include "system_rtl876x.h"
#include "rtl876x_ic_type.h"
/*============================================================================*
* Types
*============================================================================*/
/** @addtogroup RTL876x_Exported_types RTL876X Exported types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
//typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/** @} */ /* End of group RTL876x_Exported_types */
/*============================================================================*
* RTL876X Pin Number
*============================================================================*/
/** @defgroup RTL876X_Pin_Number RTL876X Pin Number
* @{
*/
#if (IC_TYPE == IC_TYPE_BEE3)
#define P0_0 0 /**> 8) |\
(((uint32_t)(x) & (uint32_t)0xff000000) >> 24)))
#define WAP16(x) ((uint16_t)(\
(((uint16_t)(x) & (uint16_t)0x00ff) << 8) |\
(((uint16_t)(x) & (uint16_t)0xff00) >> 8)))
#if SYSTEM_ENDIAN == LITTLE_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) ((uint32_t)(x))
#define rtk_le32_to_cpu(x) ((uint32_t)(x))
#define rtk_cpu_to_le16(x) ((uint16_t)(x))
#define rtk_le16_to_cpu(x) ((uint16_t)(x))
#define rtk_cpu_to_be32(x) SWAP32((x))
#define rtk_be32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_be16(x) WAP16((x))
#define rtk_be16_to_cpu(x) WAP16((x))
#endif
#elif SYSTEM_ENDIAN == BIG_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) SWAP32((x))
#define rtk_le32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_le16(x) WAP16((x))
#define rtk_le16_to_cpu(x) WAP16((x))
#define rtk_cpu_to_be32(x) ((uint32_t)(x))
#define rtk_be32_to_cpu(x) ((uint32_t)(x))
#define rtk_cpu_to_be16(x) ((uint16_t)(x))
#define rtk_be16_to_cpu(x) ((uint16_t)(x))
#endif
#endif
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile uint32_t *)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile uint32_t *)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_UPDATE32(addr, mask, value32) \
HAL_WRITE32(0, addr, (HAL_READ32(0, addr) & ~mask) | (value32 & mask))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile uint16_t *)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile uint16_t *)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_UPDATE16(addr, mask, value16) \
HAL_WRITE16(0, addr, (HAL_READ16(0, addr) & ~mask) | (value16 & mask))
#define HAL_READ8(base, addr) \
(*((volatile uint8_t *)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile uint8_t *)(base + addr))) = value)
#define HAL_UPDATE8(addr, mask, value8) \
HAL_WRITE8(0, addr, (HAL_READ8(0, addr) & ~mask) | (value8 & mask))
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#ifdef BIT
#undef BIT
#endif
#define BIT(_n) (uint32_t)(1U << (_n))
#ifdef BIT64
#undef BIT64
#endif
#define BIT64(n) (1ULL << (n))
#define BIT_BAND(reg, bit_pos) (*((volatile uint32_t*)(0x42000000 + ((uint32_t)® - 0x40000000) * 32 + bit_pos * 4)))
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
//#define USE_FULL_ASSERT
/** @} */ /* End of group RTL876X_Exported_Macros */
/*============================================================================*
* Functions
*============================================================================*/
/** @defgroup RTL876X_Exported_Functions RTL876X Sets Exported Functions
* @brief
* @{
*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : io_assert_failed((uint8_t *)__FILE__, __LINE__))
void io_assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
/**
* @brief Read data from aon register
* @param offset: register address
* @return data read from register
*/
extern uint16_t btaon_fast_read(uint16_t offset);
extern uint8_t btaon_fast_read_8b(uint16_t offset);
/**
* @brief Read data from aon register safely
* @param offset: register address
* @return data read from register
*/
extern uint16_t btaon_fast_read_safe(uint16_t offset);
extern uint8_t btaon_fast_read_safe_8b(uint16_t offset);
/**
* @brief Write data to aon register
* @param offset: register address
* @param data: data to be writen to register
* @return
*/
extern void btaon_fast_write(uint16_t offset, uint16_t data);
extern void btaon_fast_write_8b(uint16_t offset, uint8_t data);
/**
* @brief Write data to aon egister safely
* @param offset: register address
* @param data: data to be writen to register
* @return
*/
extern void btaon_fast_write_safe(uint16_t offset, uint16_t data);
extern void btaon_fast_write_safe_8b(uint16_t offset, uint8_t data);
/**
* @brief Write data to aon egister
* @param offset: register address
* @param mask: indicate which bit in data will be updated
* @param data: data to be writen to register
* @return
*/
extern void btaon_fast_update(uint16_t offset, uint16_t mask, uint16_t data);
extern void btaon_fast_update_8b(uint16_t offset, uint8_t mask, uint8_t data);
/**
* @brief Write data to aon egister safely
* @param offset: register address
* @param mask: indicate which bit in data will be updated
* @param data: data to be writen to register
* @return
*/
extern void btaon_fast_update_safe(uint16_t offset, uint16_t mask, uint16_t data);
extern void btaon_fast_update_safe_8b(uint16_t offset, uint8_t mask, uint8_t data);
/** @} */ /* End of RTL876X_Exported_Functions */
/** @} */ /* End of group RTL876X */
#ifdef __cplusplus
}
#endif
#endif /* RTL876X_H */