182 lines
7.1 KiB
C
182 lines
7.1 KiB
C
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/**
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*********************************************************************************************************
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* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
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*********************************************************************************************************
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* @file rtl876x_hw_aes.h
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* @brief
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* @details
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* @author eason li
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* @date 2016-01-04
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* @version v0.1
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* *********************************************************************************************************
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*/
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#ifndef __RTL876X_HW_AES_H
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#define __RTL876X_HW_AES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include <stdbool.h>
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#include "rtl876x.h"
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#include "hw_aes.h"
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/**
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* @brief referenc to hw aes register table
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*/
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typedef struct
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{
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union
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{
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__IO uint32_t CTL;
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struct
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{
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__IO uint32_t enc_en: 1; /* aes encryption enable */
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__IO uint32_t dec_en: 1; /* aes decryption enable */
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__IO uint32_t ase256_en: 1; /* aes 256-bit mode enable */
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__IO uint32_t aes_mode_sel: 3; /* aes mode select, see HW_AES_MODE below */
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__IO uint32_t access_mode: 1; /* 0: CPU mode, 1: DMA mode */
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__IO uint32_t scram_en: 1; /* scramble function, 0:disable, 1:enable */
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__IO uint32_t use_hidden_key: 1; /* secure related */
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__IO uint32_t copy_hidden_key: 1; /* secure related */
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__IO uint32_t hidden_256: 1; /* secure related */
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__IO uint32_t poly_en: 1; /* XOR polynomial, 0:disable, 1:enable */
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__IO uint32_t rsvd: 19;
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__IO uint32_t dout_rdy: 1; /* aes data output ready signal used in CPU mode.
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when data output is ready, dout_rdy = 1.
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if dout_rdy == 1, "CPU reads enc_dout or dec_dout
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for 4 times (128 bits)" will clear dout_rdy to 0.
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*/
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} CTL_BITS;
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};
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__IO uint32_t data_in;
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__I uint32_t enc_dout;
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__I uint32_t dec_dout;
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__IO uint32_t IRK[8];
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__IO uint32_t iv[4];
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union
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{
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__O uint32_t secure_reg[13];
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struct
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{
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__O uint32_t RPZ0_CMP_ADDR_TOP_H; /* 0x40 */
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__O uint32_t RPZ0_CMP_ADDR_TOP_L; /* 0x44 */
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__O uint32_t RPZ0_CMP_ADDR_BUTTOM_H; /* 0x48 */
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__O uint32_t RPZ0_CMP_ADDR_BUTTOM_L; /* 0x4C */
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__O uint32_t RPZ1_CMP_ADDR_TOP_H; /* 0x50 */
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__O uint32_t RPZ1_CMP_ADDR_TOP_L; /* 0x54 */
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__O uint32_t RPZ1_CMP_ADDR_BUTTOM_H; /* 0x58 */
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__O uint32_t RPZ1_CMP_ADDR_BUTTOM_L; /* 0x5C */
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__O uint32_t RPZ_SWD_CTRL; /* 0x60 */
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__O uint32_t DSP_MEM_CTRL_H; /* 0x64 */
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__O uint32_t DSP_MEM_CTRL_L; /* 0x68 */
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__O uint32_t rsvd; /* 0x6C */
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__O uint32_t reg_buf_cache_sram_en; /* 0x70 */
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};
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};
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union
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{
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__IO uint32_t secure_status;
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struct
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{
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__IO uint32_t cnt: 4;
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__IO uint32_t S: 1;
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__IO uint32_t irk_cnt: 3;
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__IO uint32_t rsvd: 8;
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__IO uint32_t hash_: 16;
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} SEC_STS;
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};
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__O uint32_t authentication;
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} HW_AES_TypeDef;
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#define HWAES_CTL 0x0
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#define HWAES_DATAIN 0x4
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#define HWAES_ENC_DOUT 0x8
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#define HWAES_DEC_DOUT 0xC
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#define HWAES_IRK 0x10
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#define HWAES_IV 0x30
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#define HWAES_SEC_REG 0x40
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#define HWAES_SEC_STS 0x74
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#define HWAES_AUTHEN 0x78
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typedef enum
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{
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CPU_MODE,
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DMA_MODE
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} HW_AES_ACCESS_MODE;
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#define DMA_CH_BASE(ChNum) (GDMA_CHANNEL_REG_BASE + ChNum * 0x0058)
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#define DMA_CH_IRQ(ChNum) ((GDMA0_Channel0_IRQn + ChNum))
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#define HW_AES_RX_DMA_IO_NUM 14
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#define HW_AES_TX_DMA_IO_NUM 13
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#define HW_AES_SET_ENC_EN(isEnable) (HWAES->CTL_BITS.enc_en = isEnable)
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#define HW_AES_SET_DEC_EN(isEnable) (HWAES->CTL_BITS.dec_en = isEnable)
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#define HW_AES_SET_256_EN(isEnable) (HWAES->CTL_BITS.ase256_en = isEnable)
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#define HW_AES_GET_256_EN (HWAES->CTL_BITS.ase256_en)
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#define HW_AES_SET_AES_MODE(mode) (HWAES->CTL_BITS.aes_mode_sel = (mode & 0x7))
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#define HW_AES_SET_WORK_MODE(mode) (HWAES->CTL_BITS.access_mode = (mode & BIT0))
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#define HW_AES_IS_DATA_OUT_READY (HWAES->CTL_BITS.dout_rdy)
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#define HW_AES_SET_INPUT_DATA(data) (HWAES->data_in = (uint32_t)data)
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#define HW_AES_READ_ENC_OUTPUT(Out) (Out = HWAES->enc_dout)
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#define HW_AES_READ_DEC_OUTPUT(Out) (Out = HWAES->dec_dout)
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#define HW_AES_SET_IRK(pIRK, cnt) for (uint8_t i = 0;i < cnt;i ++) {HWAES->IRK[(cnt - 1) - i] = pIRK[i];}
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#define HW_AES_GET_IRK(pIRK, cnt) for (uint8_t i = 0;i < cnt;i ++) {pIRK[i] = HWAES->IRK[(cnt - 1) - i];}
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#define HW_AES_SET_IV(pIV) for (uint8_t i = 0;i < 4;i ++) {HWAES->iv[3 - i] = pIV[i];}
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#define HW_AES_GET_IV(pIV) for (uint8_t i = 0;i < 4;i ++) {pIV[i] = HWAES->iv[3 - i];}
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#define HW_AES_SET_SCRAMBLE_EN(isEnable) (HWAES->CTL_BITS.scram_en = isEnable)
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#define HW_AES_USE_HIDDEN_KEY(isEnable) (HWAES->CTL_BITS.use_hidden_key = isEnable)
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#define HW_AES_COPY_HIDDEN_KEY(isEnable) (HWAES->CTL_BITS.copy_hidden_key = isEnable)
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#define HW_AES_SET_HIDDEN_256(isEnable) (HWAES->CTL_BITS.hidden_256 = isEnable)
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#define HWAES_DMA_RX_CH_NUM 2
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#define HWAES_DMA_TX_CH_NUM 1
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#define HWAES_DMA_RX_CH GDMA_Channel2
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#define HWAES_DMA_TX_CH GDMA_Channel1
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#define HWAES_DMA_RX_HANDLER GDMA0_Channel2_Handler
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#define HWAES_DMA_TX_HANDLER GDMA0_Channel1_Handler
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#define MAX_DMA_BUF_SZ 0xFF0
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#if 1
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#define AES_INFO(...) DBG_DIRECT(__VA_ARGS__);
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#else
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#define AES_INFO(...)
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#endif
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__STATIC_INLINE void hw_aes_clear(void)
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{
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HWAES->CTL = 0;
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}
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__STATIC_INLINE void hw_aes_set_clk(bool is_enable)
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{
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/* turn on hw aes clock */
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SYSBLKCTRL->u_238.BITS_238.r_PON_ACTCKE_AES = is_enable;
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/* enable hw aes */
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SYSBLKCTRL->u_218.BITS_218.r_PON_FEN_AES = is_enable;
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}
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bool hw_aes_init(const uint32_t *aesKey, uint32_t *iv, T_HW_AES_MODE work_mode, bool isAes256);
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bool hw_aes_cpu_operate(uint32_t *in, uint32_t *out, uint32_t word_len, bool isEncrypt);
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bool hw_aes_dma_operate(uint32_t *in, uint32_t *out, uint32_t word_len, bool isEncrypt,
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uint8_t dma_rx_ch_num, uint8_t dma_tx_ch_num, bool isMac);
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void hw_aes_set_dma_rx_done(bool isDone);
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bool hw_aes_is_dma_rx_done(void);
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void hw_aes_set_dma_tx_done(bool isDone);
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bool hw_aes_is_dma_tx_done(void);
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bool hw_aes_dma_done(void);
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void hw_aes_dma_interrupt_disable(void);
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void hw_aes_set_dma_move_src(uint32_t src);
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void hw_aes_set_dma_move_dst(uint32_t dst);
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void hw_aes_set_dma_carry_size(uint32_t size);
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bool aes_cmac_inverse(uint8_t *key, uint8_t *input, uint32_t length, uint8_t *mac, int mode);
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uint32_t get_secure_reg_cfg_val(uint32_t in_val);
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void share_dsp_and_cache_ram_rom(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__RTL8762X_GDMA_H*/
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